The conventional EEPROM generally has an element structure as shown in the cross-sectional view shown in FIG. 1. A drain region 1 and a source region 2 of a N-type impurity region are formed in a P-type silicon substrate 10, and a N-type impurity region 6 is formed between each of the regions 1, 2. Further, a control gate 4 is layered above the N-type impurity region 6 through a silicon oxide layer 7, and also, a floating gate 3 of a polysilicon layer is formed in the silicon oxide layer 7. This silicon oxide layer SiO.sub.2 (silicon dioxide) 7 includes a tunnel insulation layer 8 thinner than the rest of the layer 7, so that electrons formed in the N-type impurity region 6 are caused to be injected into the floating gate 3 where the electrons are accumulated, and to be drawn from the layer 3 via the tunnel insulation layer 8 by utilizing the tunnel effect. Further, a select gate 5 is layered on the silicon oxide layer 7 between the N-type impurity region 6 and drain region 1.
FIG. 2 shows a partial expanded structure, which is enclosed by the dotted line A shown in FIG. 1, including the tunnel insulation layer 8 and part of the floating gate 3. The structure shown in FIG. 2 is formed by a method explained below in connection with FIGS. 3(a)-3(d).
As shown in FIG. 3(a), a silicon oxide layer 27 is layered on the entire surface of the silicon substrate 10 having N-type impurity 6, and part of the silicon oxide layer 27 is removed by a photolithographic process to expose a surface region 28 of part of the silicon substrate 10, in order subsequently to form the tunnel insulation layer 8 (FIG. 3(b)). Further, the tunnel insulation 8 is formed on the surface of the exposed substrate (FIG. 3(c)), and the polysilicon layer 3 is layered on the silicon layers 7 and 8. A phosphorus impurity is diffused in the polysilicon layer 3 by being placed in an atmosphere of POC13, in order to improve the conductivity of the polysilicon layer 3 (FIG. 3(d)).
However this semiconductor memory device has the following drawbacks.
As shown in FIG. 3(b), when part of the silicon oxide layer 27 is removed by the photolithographic process and is exposed in order to subsequently form the tunnel insulation layer 8, after the silicon oxide layer 27 is layered on the entire surface of the silicon substrate 10, the surface 28 of the exposed substrate 10 is contaminated, because a photoresist is removed by a solution including H.sub.2 SO.sub.4 and H.sub.2 O.sub.2 with the surface exposed. As a result, the dielectric breakdown voltage of the tunnel insulation layer 8 is remarkably lowered. To prevent the above drawbacks, a process of dipping into a diluted HF solution is carried out before the tunnel insulation layer 8 is formed on the exposed surface 28 of the substrate 10. Although the dielectric breakdown voltage of the tunnel insulation layer 8 is increased, that of the oxide layer 7 is lowered because the silicon oxide layer 7 itself is exposed to diluted HF solution. Also, in the process step of FIG. 3(d), the phosphorus is diffused in the polysilicon layer 3. But the dielectric breakdown voltage of the tunnel insulation layer 8 too is lowered because phosphorus is also diffused into the insulation layer 8.
With regard to a method of examination TDDB (Time Dependent Dielectric Breakdown) into the dielectric breakdown voltage of the tunnel insulation layer 8, there is the method of applying a constant current to the tunnel insulation layer 8. By this method, the rate of defective products generated after the passage of a certain time is examined. And, with regard to a method of examination into the dielectric breakdown voltage of the silicon oxide layer 7, there is the method of applying a voltage between the select gate 5 and the silicon substrate 10 while the part of the silicon oxide layer 7 between them is destroyed. By this method, the rate of products destroyed by an applied voltage of 20 V or less is examined. However, it is not possible to obtain good results by performing both examinations due to the above drawbacks.